By Tsutomu Miki
Discusses a 'bio-inspired' implementation of human-brain laptop structure referred to as brainware, via eight papers from an IIZUKA convention held in 1998. Serves as a reference for graduate scholars and thought for additional examine at the subject.
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Additional resources for Brainware : Bio-Inspired Architecture and Its Hardware Implementation
Ikebe, and Y. Amemiya, "A vMOS Cellular-Automaton Device for Differential-of-Gaussian Filtering," Extended Abstract of the 1999 International Conference on Solid State Device and Materials, Tokyo, 1999, pp. 110-111.  T. Shibata, M. Yagi, and M. 648-656, Sunnyvale, California, July 68, 1999. Chapter 2 Adaptive Learning Neuron Integrated Circuits Using Ferroelectric-Gate FETs Sung-Min Yoon, Eisuke Tokumitsu, and Hiroshi Ishiwara Tokyo Institute of Technology Abstract An adaptive-leaning neuron circuit composed of MFSFET and complementary unijunction transistor (CUJT) oscillation circuit was fabricated on an SOI (siliconon-insulator) structure as the first step to the next-generation neural network.
A photomicrograph of the analog VQ processor chip is shown in Fig. 23. 2mm. A single chip contains 256 16-element template vectors. 6-jim CMOS technology) if it is assumed that the chip size scales with die minimum feature size of the technology. 2. Fully Parallel Motion-Vector Detection Circuitry [33, 22] The basic architecture of the vector matching circuitry in the vMOS association processor (Fig. 15) has been applied to the motion vector detection, or motion compensation, the most time consuming processing in the MPEG-2 coding.
9. From these results, it is concluded that the MFSFET was successfully fabricated under the new wet etching condition, and that the obtained memory window is due to the ferroelectricity of SBT film, obviously. The memory effect was also shown from drain current (ID) - drain voltage (VD) characteristics for the same FET, as shown in Fig. 10. First, Adaptive Learning Neuron Integrated Circuits ... 2 < io-' Fig. 9 i 1 102 103 10 4 10 Gate Voltage Sweep Rate (V/s) 105 Dependence of memory window width on the sweep rate of gate voltage.
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